Avoiding common scalability pitfalls in shared-cache chip multiprocessor design

Abstract

Today, the most common approach to next-generation microprocessor design is to increase their core number. However, in general-purpose microprocessors, the growing performance disparity between DRAM and the cores, and the need to retain compliance with common paradigms, including coherent shared memory and unifirm memory access, lead to a number of issues as the number of cores scales up.In this work, we duscuss some of the common scalability issues in such processors, involving shared cache, on-chip network, and DRAM controller design, and propose their solutions suitable for at least 1000-core chip multiprocessors according to the results of our analysis and experiments.