Accelerating STT-MRAM Ramp-up Characterization

Abstract

Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.