A PROLOG-based connectivity verification tool

Abstract

A connectivity verification program implemented in PROLOG is presented. The major advantage of this program, called VERCON, over existing approaches is that it always works, irrespective of circuit topology. VERCON's approach to connectivity verification is to extract all the different designer-specified subcircuits from the flat transistor description. Verification is achieved when the top-level object is extracted and there are no transistors which were not used to form the top-level object. Although VERCON is a research prototype, several valuable conclusions have been drawn that will aid the design of a connectivity verification program written in C.<>