Embedded SRAM trend in nano-scale CMOS

Abstract

This paper describes an SRAM scaling trend in terms of bit-cell size and operating voltage (Vdd) in a nano-scale process generation. The key design solutions to extend a 6T SRAM lifetime are reviewed and discussed including a possible bit cell scaling trend comparing with an 8T SRAM as one of the successors. Each dependency of 3 key margins of write margin (WRM), static noise margin (SNM), and cell current (Icell) on the scaling ratio of Vdd and MOSFET channel feature size has been shown to clarify the real issues in the scaling. The bit cell area scaling trends of 6T and 8T SRAMs are predicted. It has been shown that the area of 6T will be getting closer to that of 8T at 32 nm and should cross over around 22 nm.