Power integrity analysis for core timing models

Abstract

An improved framework of power integrity analysis for core logic timing analysis is presented in this paper. Due to ever increasing power consumption of core digital blocks, jitter due to supply noise contributes a significant timing error, and on-chip logic timing analysis requires accurate modeling of supply noise induced jitter. Jitter information provides additional information to define precise power distribution network (PDN) requirements. The formulation to predict the jitter due to core noise is first presented in this paper followed by the modeling flow that can conveniently be incorporated into existing static timing analysis (STA) analysis. The presented method accounts for potential jitter tracking or anti-tracking between data and clock paths and any AC noise behavior. It covers a general topology including unbalanced clock trees, multi-cycle data paths, and multiple-power domains.