Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack

Abstract

A continuous scaling down of technology drives the microelectronics industry towards the nanoscale regime, wherein various fabrication-related defects such as electromigration induced open/short faults, interfacial cracks, and thermal stress-induced leakage problems primarily dominate the overall performance of a through silicon via (TSV). Interfacial cracking plays a pivotal role in the long-term service reliability of the chip among them. On account of these facts, this paper provides equivalent RLGC fault modeling and performance analysis of thermo-mechanical delamination in TSVs known as interfacial cracks. Considering the MOS effect, an analytical expression is derived using defective parameters to analyze the feasibility and reliability of the defected TSVs at different crack widths and heights. Using a driver-via-load (DVL) setup, performance in terms of power dissipation, power delay product (PDP), and dynamic crosstalk delay are analyzed using a CMOS driver. Encouragingly, considering interfacial cracked TSV, power and crosstalk delay are improved by 74.4% and 65.5%, respectively, at a minimum crack length approaching the defect-free condition.