Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency

S. Manohar, R. Venkatasubramanian, P. Balsara
{"title":"Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency","authors":"S. Manohar, R. Venkatasubramanian, P. Balsara","doi":"10.1109/VLSID.2012.74","DOIUrl":null,"url":null,"abstract":"Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip DC-DC converters. As a feasibility study of using NEMS in integrated power electronics, discontinuous conduction mode (DCM) buck regulator with specifications suitable for portable applications has been implemented in a NEMS-CMOS hybrid design and the results are compared against a standard commercial 0.35 μm CMOS implementation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5-10nm. This work shows that NEMS-CMOS hybrid DC-DC converter has an area savings of 60V over CMOS and achieves 95% efficiency at max load condition (50mA).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.74","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip DC-DC converters. As a feasibility study of using NEMS in integrated power electronics, discontinuous conduction mode (DCM) buck regulator with specifications suitable for portable applications has been implemented in a NEMS-CMOS hybrid design and the results are compared against a standard commercial 0.35 μm CMOS implementation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5-10nm. This work shows that NEMS-CMOS hybrid DC-DC converter has an area savings of 60V over CMOS and achieves 95% efficiency at max load condition (50mA).
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于提高面积和功率效率的混合NEMS-CMOS DC-DC变换器
纳米机电(NEM)继电器是一类很有前途的新兴器件,具有零泄漏操作。NEM继电器逻辑电路的终端应用最近被提出了很多[1][2]。本研究探讨了NEM继电器在片上DC-DC转换器中的应用。作为在集成电力电子中使用NEMS的可行性研究,在NEMS-CMOS混合设计中实现了规格适合便携式应用的不连续传导模式(DCM)降压调节器,并将结果与标准商用0.35 μm CMOS实现进行了比较。NEM继电器开关的Ron是恒定的,对栅极压转率不敏感。这创造了电源开关设计的范式转变。这与无限Roff相结合,与CMOS相比具有显着的面积和功率优势。精确的Verilog-A模型是基于已发表的NEM继电器[1]的制造结果开发的,工作电压为1V,标称气隙为5-10nm。这项工作表明,NEMS-CMOS混合DC-DC转换器比CMOS节省60V的面积,在最大负载条件下(50mA)达到95%的效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Two Graph Based Circuit Simulator for PDE-Electrical Analogy Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems Efficient Online RTL Debugging Methodology for Logic Emulation Systems Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1