Improved digital calibration technology in a 12-b, 40-MS/s pipelined ADC

Abstract

In the design of 12-bits 40MSample/s pipelined ADC, the traditional close-loop high performance residue amplifier in first stage is replaced by an open-loop amplifier to reduce power dissipation and increase circuit speed. The errors brought by open-loop amplifier are evaluated and calibrated by an improved statistics-based background calibration technology. A self-adaptive search algorithm and a magnitude incremental comparison algorithm are presented in statistics-based background calibration technology to improve residue difference estimator circuit and LUT (look up table) of binary monotonically function respectively. The improved calibration technology can reduce digital circuit power dissipation and size significantly. Simulation results show that power consumption of digital circuit is reduced by 93% and room of ROM is saved by 84%. The ADC is implemented in SMIC 0.18 CMOS process, consumes 210 mW, and has a layout size of 3.2*3.7 mm2.