A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers

Abstract

Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-VT sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V