{"title":"Optimal synthesis of digital counter","authors":"H. Javan, V. Rayaravivarma","doi":"10.1109/SOUTHC.1996.535107","DOIUrl":null,"url":null,"abstract":"This paper presents a unified and systematic approach to the analysis and synthesis of digital counters. Our method consists, firstly of analysing a given 3 bit counter to develop the state diagram and to investigate the possibility of hangup states. Based on this, we then synthesized a given logic function. Different synthesis methods are discussed, compared, and finally, an optimum circuit meeting the design specifications is selected.","PeriodicalId":199600,"journal":{"name":"Southcon/96 Conference Record","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Southcon/96 Conference Record","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOUTHC.1996.535107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
This paper presents a unified and systematic approach to the analysis and synthesis of digital counters. Our method consists, firstly of analysing a given 3 bit counter to develop the state diagram and to investigate the possibility of hangup states. Based on this, we then synthesized a given logic function. Different synthesis methods are discussed, compared, and finally, an optimum circuit meeting the design specifications is selected.
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