Large scale atm multi-stage switching network with shared buffer memory switches

Abstract

This paper discusses the configuration of an ATM(Asynchronous Transfer Mode) switching network with a shared buffer memory switch (SBMS) which has the potential to provide good traffic characteristics and easy LSI implementation. The scaling factors of the ATM switching network under a condition of mixed applications are discussed first. Then the SBMS as the unit element ofthe multi-stage switching network is described, and its performance evaluation and experimental data are introduced. The data indicate excellent performance under burst cell arrival condition. Last a concept of a large scale ATM switching network configuration with multi-stage switches is proposed. The non blocking condition in ATM multi-stage switching network as an alternative resource management scheme is described.