CAPE-VLSI implementation of a systolic processor array: architecture, design and testing

Abstract

The singular value decomposition (SVD) is an important matrix factorization used in a variety of applications. The SVD exhibits better numerical stability due to the insensitivity to ill-conditioning or rank deficiency of matrices. However, the SVD is computationally intensive. The CORDIC array processor element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (coordinate rotation digital computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabrication service. Experienced gain from designing the prototype helped in the design of integrated single-chip version. The chip has been implemented on a 5600*6900 mu die in a 2 mu n-well scalable CMOS process.<>