A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm CMOS

Abstract

This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13µm CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the −1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively.