A. Portero, G. Talavera, M. Montón, Borja Martínez, Marc Moreno, F. Catthoor, J. Carrabina
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引用次数: 2
Abstract
Developers of next generation Multi-Processor Systems-on-a-chip (MPSoC) silicon platforms used in multimedia mobile devices should design efficient systems for diverse execution time vs. energy consumption trade-offs for a given quality of service. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can obtain singular computational/power trades offs points and thus design energy efficient platforms. This paper presents a high level methodology to acquire an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a MPEG-4 encoder described in C++ language which is translated to a SystemC hard/soft description which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (CRISP-Trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a classic DSP.