Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA

Abstract

Floating-point fast Fourier transform (FFT) processor and coordinate rotation digital computer (CORDIC) element play important roles in communication and radar applications. But even with the rapid development of large-scale integrated circuit, it is usually impractical to implement these floating-point computations on FPGA, as they will consume a large amount of chip resources. In this paper, a compact SAR processor, composed of four 1D FFT-PEs (processing elements) and a CORDIC co-processor, is implemented on FPGA. In particular, a dynamic configurable pipeline is used in FFT-PE to reduce the area consumption through reusing floating-point units. And the 32-bit floating-point hybrid-mode CORDIC co-processor is implemented to generate compensation factors and compute transcendental functions in SAR image visualization phase. Experimental results show that our SAR processor performs well both in area and latency. It consumes about 40% of LUTs and DSPs, and about 48% of memory bits on a StratixII FPGA. Moreover, 32-bit floating-point hybrid-mode CORDIC co-processor only occupies about 2.6% LUTs and Registers of Virtex5 and achieves a clock frequency of 217 MHz. Regarding the latency, it takes 1232.6 ms to transform the SAR raw data of 4K*4K into a visible image of 256 grey levels and can meet the real-time requirement.