Double pulse test method for neutral point clamped inverter switches at the nominal rating while using only half of the nominal DC link voltage

Abstract

Double pulse test is the industry standard for determining the switching characteristics of a semiconductor switch. The component manufacturers implement the double pulse test with a dedicated test setup with favorable layout for minimizing the switching loop inductance. Such layout and minimized loop inductances may not be implemented with different inverter topologies. Therefore, independent tests must be done for each switch of the phase-leg to ensure the switching behavior for each possible commutation loop. This procedure becomes more critical with more complex phase-leg structures of multilevel inverters. This paper presents a double pulse testing method dedicated for a phase-leg of a three-level neutral point clamped inverter. With the proposed method, all of the commutation loops within the phase-leg can be tested at nominal voltage rating with half of the nominal DC link voltage as input. The method is verified with experimental results using a phase-leg of a medium voltage three-level neutral point clamped inverter using 4.5 kV rated insulated-gate bipolar transistors.