Compiling to the gate level for a reconfigurable co-processor

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI:10.1109/FPGA.1994.315607

WO David, Kevin Forward

引用次数: 21

Abstract

This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation.<>

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编译到可重构协处理器的门级

本文介绍了一种可编程协处理器。编写了一个C编译器，可以将C代码编译到门级，减轻了程序员编写协处理器的繁重工作。由于并非大多数C程序中的所有代码都适合FPGA的协处理器，因此程序首先使用标准的C编译器进行编译。然后对这些程序进行分析，以确定代码的哪些部分最频繁地使用处理器。然后将这些部分编译到门级并在协处理器中实现。通过与IPC Sparcstation的比较，该方法可使程序执行时间加快约20%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines

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