{"title":"An area-time-efficient residue-to-binary converter","authors":"Wen Wang, M. Swamy, M. Ahmad","doi":"10.1109/MWSCAS.2000.952900","DOIUrl":null,"url":null,"abstract":"In this paper, a new residue-to-binary conversion algorithm, that reduces the size of modulo operation required by the Chinese remainder theorem, is introduced. Based on this algorithm, an efficient residue-to-binary converter is proposed for a general residue number system. The proposed converter achieves a significantly better performance in terms of area, time, and power consumption than existing devices. For the case of the 28-bit dynamic range, the proposed converter is about 20% faster while requiring only 70% of the area, compared to the best existing converter (Srikanthan et al, IEE Proc. Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, 1998). Also, the power consumption is reduced by 16% in high speed situations and 50% in low voltage situations.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.952900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
In this paper, a new residue-to-binary conversion algorithm, that reduces the size of modulo operation required by the Chinese remainder theorem, is introduced. Based on this algorithm, an efficient residue-to-binary converter is proposed for a general residue number system. The proposed converter achieves a significantly better performance in terms of area, time, and power consumption than existing devices. For the case of the 28-bit dynamic range, the proposed converter is about 20% faster while requiring only 70% of the area, compared to the best existing converter (Srikanthan et al, IEE Proc. Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, 1998). Also, the power consumption is reduced by 16% in high speed situations and 50% in low voltage situations.
本文提出了一种新的残数到二值的转换算法,该算法减小了中国剩余定理所要求的模运算量。在此基础上,提出了一种适用于一般残数系统的有效残数-二进制转换器。所提出的变换器在面积、时间和功耗方面都比现有器件有显著的提高。对于28位动态范围的情况,与现有最佳转换器(Srikanthan等人,ieee Proc. Comput)相比,所提出的转换器的速度约为20%,而占地面积仅为70%。数字。技术,第145卷,第145号。3,页229-235,1998)。此外,在高速情况下功耗降低16%,在低压情况下功耗降低50%。