Study of Turns Impact on ESD-immunity of High-voltage nLDMOSs with a Constant Floating-poly

Abstract

A TSMC $0.18- \mu \mathrm{m}50 -\mathrm{V}$ process is used to realize high-voltage nLDMOS devices. The floating-poly (poly-2) shows a spiral shape in the layout diagram. Commonly, the electric field in an nLDMOS decreases if the area is occupied by the poly-2 increases. However, the method used in this study is to increase or decrease the number of turns with the same occupied area of poly-2. Therefore, we studied whether the electric field rises or falls depending on the number of turns or the area occupied without changing the area occupied by poly-2. The reference device had the poly-2 with seven turns, and the other groups had 9 turns or 3 and 5 turns. Eventually, the highest electric field of the 9-turn device was 2.76 x 108 (V/cm), and its occupied area is the most dispersed distribution. For the 3 circles device is the most concentrated, the lowest electric field is 3.39 x 106 (v/cm). If the occupied area remains unchanged, the electric field is greatly reduced with the concentrated poly-2.