A synchronous modular multiplier with variable latency

Abstract

Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.