Performance analysis of multiplication operation based on vedic mathematics

Abstract

In this work the authors proposed a multiplier circuit which is one of the important hardware block in most of the digital and high performance systems such as ALU in the microprocessors and controllers. Multiplication is one of the most time consuming operation as a number of bit increase multiplication become cumbersome in the processors. The multiplier architecture proposed in this paper is based on the urdhva triyakbham sutra of ancient Indian Vedic mathematics (vertical and crosswise). The effectiveness of this method is to be tested against the conventional multiplication in mathematics with the focus as easy and faster multiplication. The number of digits varied and the algorithm is tested for its suitability over conventional multiplier. The results are tabulated in term of number of gates, time required for multiplication with respect to number of digits.