A Charge Tramfer Amplifier And Am Encoded Bus Aditectum For Low Power SRAM

Abstract

We proposed and tested a low power SRAM using charge transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier compensates the Vth mismatch between the pair MOS transistors, and the encoded bus signal reduces the number of wires being switched. They are dynamically controlled by a low power DLL we proposed. The fabricated SRAM worked at 5OMHz with the power dissipation of 5mW at 1V power supply. Introduction The conventional SRAM latch amplifiers, whose inputs are reset to VDD/2, have delay proportional to l/(VDD/2Vth), thus suffer much severely from VDD reduction in terms of the sensing delay increase. Furthermore, the Vth and Id variations in the pair MOS transistors can not be neglected in the sense amplifier design in the deep submicron technology era, because of increased process-origin electric characteristics variations and the reduced bit-line swing due to a small cell current. The following simulations and results are based on our 0.35-pm multi-Vth CMOS technology. A Charge-Tmfer Pre Amplifier The CT amplifier has a pronounced sensitivity and consumes small power. In a balanced use [I], it compensates the Vth mismatch of the two CT MOS transistors, and its incomplete precharge operation gives a switching time of a few ns (Fig.l(a)). We modified the CT-gate pulse to disconnect bit-lines before the latch operation, reducing the bit-line swings to decrease the bit-line charging power and increase the laich speed (Fig.l(b)). The bit-line precharge is performed using 1.5V precharge source, because low voltage SRAM needs bit-line potentials to be kept near VDD (=1V) for the cell stability. The gm improvement in a MOS technology with Tox= 5.5nm, the pulling up the bit lines to IV, and the differential signal scheme in SRAMs reduced the precharge period to 2.5ns, which is fast enough for a 5OMHz operation. Fig. 3(a) shows the simulated waveforms of the CT amplifier, whose circuit implementation is illustrated in the upper half of the Fig. 4. The CT amplifier is operated following the sequence, (1) through (6). First, (1) precharge bit-lines to lV, (2) further precharge the bit-lines towards 1 SV-Vth level through the nMOS CT gates, and (3) turn off the pull-up PMOS at the CT drains and activate a word-line. This makes the BL1 become lower than /BL1 due to a cell current and BI lowers faster than /B1, because Vgs-Vth of the CT on BL side is larger. (4)-(5) activate the nMOS cross coupled sense latch, and finally (6) precharge the bit-lines, B 1 and /B 1, for next cycle. At the beginning of (3), the incomplete bit-line charging is enough to overcome a mismatch or an offset of the sense latch as large as 0.1 V. Since the nMOS dynamic latch is activated at Vgs=VDD in the period (4), its delay is two times shorter than that of a half-VDD-precharge CMOS latch. The proposed CT amplifier consumes less current, which is 12.6pA with 1.5V power supply at SOMHz. With the penalty of the clocking powers, they consumes 580pW at 5OMHz for 16 bits. An Encoded Bus and its Transceiver and Receiver In our 16-bits bus, the power consumption is reduced to a quarter both by using a reduced-voltage-swing signal and by a reduced number of signal wires. Fig. 2 compares three types of bus driving architectures. In the proposed scheme, two sense latches are paired and one of the four precharged bus lines is pulled down with the PMOS pass-gate encoder (Fig.2(c)). The pass-gates are immediately turned on by the sense latch activation only in an active block. The use of an nMOS transfer (Fig. 2(a)) requires no clocks, but bus swing is large. PMOS transfer gives a rapid decrease in the bus potential at the beginning within a limited swing, but needs a selection clock (Fig. 2(c)). See Fig.3(b) and the middle of Fig.4 for details. Table 1 summarizes the logical assignment in the encoded bus. At the receiving circuit as in the bottom of Fig. 4, two of CMOS latches with the nMOS sourcefollower decode the bus to 2 bits. The inserted series nMOS sets its bottom source voltage to Vlow-Vth,where Vlow is the bus's low level. Thus, they act as AND. The series nMOS are divided into two and their gates are crossed so as to cancel the source resistance effect. The receive latches are modified from DSL circuit [2]. The total of power estimation for 16bits concerning to the bus was 480pW at 5OMHz. An 8 stages DLL scheme We employ an eight phase DLL circuit to control the CT amplifiers and other dynamic circuits. Each delay unit has two stages of clocked CMOS inverter VC delay and four stages of normal inverters, and consumes 6.IpA. This is less than that of a six stages of VC delay, which is 9.1 pA. The DLL consumes 150pW at hot standby, 1mW at active, and needs 10 cycles to lock in from cold standby. Experimental Results Tables 2 and 3 summarize process parameters and chip organization respectively. The SRAM achieved the main clock access time of 17ns at VDD=lV and SVDD=l.SV with 5mW power consumption at a writelread of 50%. Fig.5 shows a micro-photograph of the chip. The cell array consists of 8 blocks and in a block, 16bit-line pairs were directly connected to 16 CT amplifiers. Also, a boosted pulsed-wordline scheme and an MT-CMOS [3] powerdown technique were used. Conclusion The combination of the proposed CT amplifier, encoded bus, and DLL circuits meet requirements for medium speeds and low voltage low power SRAMs employing the deep submicron technologies. ferences [ 11 L. G. Heller et al., IEEE JSSC, 11, p. 596( 1976). [2] L. Pfennings et al., IEEE JSSC, 20, p. 1050( 1985). [3] S. Date et al., IEEE Symp. Low Power Electron. Conf p. 90(1994) 77 4-93081 3-76-X 1997 Symposium on VLSl Circuits Digest of Technical Papers WL n CT ( VR.PC 3-43