{"title":"Design automation system and architecture for high-performance integer applications","authors":"S.G. Smith, R. Morgan, J. Payne","doi":"10.1109/ASIC.1989.123210","DOIUrl":null,"url":null,"abstract":"A CAD system for design and synthesis of high-performance processors tailored to digital signal processing (DSP) applications is described. A unique design capture system supports independent specification of processor function, throughput, and accuracy, while a powerful circuit generation system isolates designers from details of the processor implementation. Circuits are assembled automatically according to an architectural blueprint, which is flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. The authors illustrate some multiplier instances in the parameter space and provide several snapshots from a design case study.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A CAD system for design and synthesis of high-performance processors tailored to digital signal processing (DSP) applications is described. A unique design capture system supports independent specification of processor function, throughput, and accuracy, while a powerful circuit generation system isolates designers from details of the processor implementation. Circuits are assembled automatically according to an architectural blueprint, which is flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. The authors illustrate some multiplier instances in the parameter space and provide several snapshots from a design case study.<>
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