VLSI Implementation of 1/2 Viterbi Decoder for IEEE P802.15-3a UWB Communication

Abstract

This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace- back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.