Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme

Abstract

A new interleaved synchronous mirror delay (SMD) is proposed in order to reduce the circuit size. The conventional interleaved SMD has multiple pairs of forward delay array (FDA) and backward delay array (BDA) in order to reduce the clock skew. The proposed interleaved SMD requires one FDA and one BDA by changing the position of MUX. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on 0.25 /spl mu/m two-metal CMOS technology.