{"title":"The Harris video teleconferencing chip set","authors":"D. Chester","doi":"10.1109/SOUTHC.1996.535136","DOIUrl":null,"url":null,"abstract":"The hardware portion of the Harris Semiconductor Personal Computer Multimedia System is a five chip set which implements, in conjunction with a host processor and associated software and firmware, a complete H.320 video teleconferencing capability over ISDN 2B lines. The chip set is comprised of a PAL/NTSC video encoder, a PAL/NTSC video decoder, a video codec, a bus interface and audio processor chip, and an audio codec. All five chips in the set are implemented in a 0.5 or 0.6 micron CMOS process. Each of the chips implement digital signal processing algorithms of varying levels of complexity and flexibility. These levels range from standard interpolation and decimation filter implementations found on the audio codec to dual programmable digital signal processor cores found on the bus interface and audio processor chip.","PeriodicalId":199600,"journal":{"name":"Southcon/96 Conference Record","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Southcon/96 Conference Record","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOUTHC.1996.535136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The hardware portion of the Harris Semiconductor Personal Computer Multimedia System is a five chip set which implements, in conjunction with a host processor and associated software and firmware, a complete H.320 video teleconferencing capability over ISDN 2B lines. The chip set is comprised of a PAL/NTSC video encoder, a PAL/NTSC video decoder, a video codec, a bus interface and audio processor chip, and an audio codec. All five chips in the set are implemented in a 0.5 or 0.6 micron CMOS process. Each of the chips implement digital signal processing algorithms of varying levels of complexity and flexibility. These levels range from standard interpolation and decimation filter implementations found on the audio codec to dual programmable digital signal processor cores found on the bus interface and audio processor chip.
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