{"title":"Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors","authors":"Soohong P. Kim","doi":"10.1109/MTV.2005.19","DOIUrl":null,"url":null,"abstract":"This paper presents a pre-silicon validation methodology of Intelreg Itaniumreg processor family (IPF) memory ordering for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Sixth International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2005.19","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a pre-silicon validation methodology of Intelreg Itaniumreg processor family (IPF) memory ordering for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage