T. Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, W. Rim, S. Baek, Sangyeop Baeck, Jonghoon Jung
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引用次数: 2
Abstract
3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.
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