{"title":"The Huge Microphone Array. 2","authors":"H. Silverman, W. Patterson, J. Flanagan","doi":"10.1109/4434.749134","DOIUrl":null,"url":null,"abstract":"The Huge Microphone Array project began in February 1994 to design, construct, debug, and test a real-time 512-microphone array system and to develop algorithms for it. Analysis of known algorithms indicated that signal-processing performance of over 6 Gflops would be required, while the need for portability--fitting it into a small van--also set an upper limit to the power required. These tradeoffs and many others have led to a unique design in both hardware and software. This two-part article presents the full design and its justifications. The authors also discuss performance for a few important algorithms relative to usage of processing-capability, response latency, and difficulty of programming. The first article in the last issue described system planning and design, while this issue's follow-up article describes the system itself.","PeriodicalId":282630,"journal":{"name":"IEEE Concurr.","volume":"280 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Concurr.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/4434.749134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
The Huge Microphone Array project began in February 1994 to design, construct, debug, and test a real-time 512-microphone array system and to develop algorithms for it. Analysis of known algorithms indicated that signal-processing performance of over 6 Gflops would be required, while the need for portability--fitting it into a small van--also set an upper limit to the power required. These tradeoffs and many others have led to a unique design in both hardware and software. This two-part article presents the full design and its justifications. The authors also discuss performance for a few important algorithms relative to usage of processing-capability, response latency, and difficulty of programming. The first article in the last issue described system planning and design, while this issue's follow-up article describes the system itself.