End-to-End Multi-Target Verification Environment for a RISC-V Microprocessor

Abstract

In this paper, we present the end-to-end verification environment developed for verifying A-Core, a custom, extensible and configurable RISC-V microprocessor targeted for controlling communication, cryptography, and machine learning hardware accelerators. The developed open source verification environment utilizes a Python-based ASIC-generic system verification framework. In the developed environment, the processor can be verified with self-checking user-written Assembly- or C-programs, providing a seamless from-C-to-hardware verification methodology. With the presented test platform, test programs can be run on various targets: RTL simulation, FPGA, or ASIC, providing one verification environment for all maturity levels of the design. The platform enables end-to-end testing: verification of the functionality of the A-Core ASIC from the programming sequence over a JTAG interface to printouts over UART, providing tests coverage also for real use cases of the hardware. Performance metrics for different sized test programs are provided to enable characterization of the speed of verification.