{"title":"A bit scalable architecture for fuzzy processors","authors":"R. d'Amore, K. Heinz Kienitz, O. Saotome","doi":"10.1109/SBCCI.1999.802957","DOIUrl":null,"url":null,"abstract":"Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. This paper presents bit scalable architecture that allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description. The size of the internal units is defined from a small number of parameters in the highest level entity.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"4 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.1999.802957","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. This paper presents bit scalable architecture that allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description. The size of the internal units is defined from a small number of parameters in the highest level entity.
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