{"title":"Kahn process networks applied to distributed heterogeneous HW/SW cosimulation","authors":"Dylan Pfeifer, J. Valvano","doi":"10.1109/ESLSYN.2011.5952290","DOIUrl":null,"url":null,"abstract":"Heterogeneous, distributed hardware/software cosimulation techniques using the backplane method encounter complex interface protocols for simulator communication and synchronization, limiting their adoption or abstraction. We simplify the dynamics of backplane cosimulation to the properties of a Kahn Process Network (KPN), such that tokens of the KPN are interpolated events. This simplifies the backplane API and reduces the coordination problem to a parameterization of token update rates. The performance of this method is reported on a timed ISS model for Freescale HC12 microcontrollers (TExaS) coordinated with a Spice (Ngspice) circuit simulation.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Electronic System Level Synthesis Conference (ESLsyn)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESLSYN.2011.5952290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Heterogeneous, distributed hardware/software cosimulation techniques using the backplane method encounter complex interface protocols for simulator communication and synchronization, limiting their adoption or abstraction. We simplify the dynamics of backplane cosimulation to the properties of a Kahn Process Network (KPN), such that tokens of the KPN are interpolated events. This simplifies the backplane API and reduces the coordination problem to a parameterization of token update rates. The performance of this method is reported on a timed ISS model for Freescale HC12 microcontrollers (TExaS) coordinated with a Spice (Ngspice) circuit simulation.