{"title":"A 0.3mW 1.4mm2 Motion Estimation Processor for Mobile Video Application","authors":"S. Hiratsuka, S. Goto, T. Ikenaga","doi":"10.1109/ASSCC.2006.357862","DOIUrl":null,"url":null,"abstract":"Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-mum CMOS technology. 15 K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/ sec ME processing.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-mum CMOS technology. 15 K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/ sec ME processing.