{"title":"Scaling perspective for III-V broken gap nanowire TFETs: An atomistic study using a fast tight-binding mode-space NEGF model","authors":"A. Afzalian, M. Passlack, Y. Yeo","doi":"10.1109/IEDM.2016.7838510","DOIUrl":null,"url":null,"abstract":"We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space (MS) technique with large speedup (up to 250×) while keeping good accuracy (error < 1%). It is shown that both n- and pTFET performances are best above 20 nm gate length for a cross-section of 5.5 nm in the [111] crystal orientation. At V<inf>dd</inf> = 0.3 V and I<inf>off</inf> = 50 pA/μm, the on-current (Ion) and energy-delay product (ETP) gain over a Si NW GAA MOSFET are 58× and 56× respectively. In a beyond 5 nm node low power ITRS 2.0 horizontal GAA design rule however, where the gate length is restricted to 12 nm, a [100] orientation is best but features up to 3× I<inf>on</inf> and 2.4× ETP degradation vs. the 20 nm TFET GAA design.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2016.7838510","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space (MS) technique with large speedup (up to 250×) while keeping good accuracy (error < 1%). It is shown that both n- and pTFET performances are best above 20 nm gate length for a cross-section of 5.5 nm in the [111] crystal orientation. At Vdd = 0.3 V and Ioff = 50 pA/μm, the on-current (Ion) and energy-delay product (ETP) gain over a Si NW GAA MOSFET are 58× and 56× respectively. In a beyond 5 nm node low power ITRS 2.0 horizontal GAA design rule however, where the gate length is restricted to 12 nm, a [100] orientation is best but features up to 3× Ion and 2.4× ETP degradation vs. the 20 nm TFET GAA design.