A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation

Steven Callender, A. Niknejad
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引用次数: 8

Abstract

This paper presents the design of a 1 GHz Delay-Locked Loop (DLL) with embedded phase interpolation. The DLL was designed in a 0.13µm SiGe BiCMOS process and provides a measured single-tap phase range of 50ps (18°) with an average and worst-case phase resolution of 1.36ps (0.49°) and 5ps (1.8°), respectively. This translates to beamsteering resolutions of < 3.5mm in free space when integrated into mm-wave imagers that utilize time-domain beamforming. The DLL has an average output rms-jitter (across all interpolation steps) of 860fs. The DLL consumes 33 mW of power and occupies an area of 0.185mm2.
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利用嵌入式相位插值的相位可调延迟锁相环
本文设计了一种内置相位插值的1ghz延时锁相环(DLL)。DLL采用0.13 μ m SiGe BiCMOS工艺设计,可提供50ps(18°)的单相测量范围,平均和最差相位分辨率分别为1.36ps(0.49°)和5ps(1.8°)。这意味着波束转向分辨率为<当集成到利用时域波束形成的毫米波成像仪中时,自由空间为3.5mm。DLL的平均输出均方根抖动(跨所有插值步骤)为860fs。DLL的功耗为33 mW,占地面积为0.185mm2。
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