Self-aligned Ohmic And Self-Aligned Implant GaAs Gate FET With Integrated Diode

Abstract

Recently there has been increased interest in semiconductor-gate heterostructure FETs [l-41, due to their potentially uniform threshold voltages, as well as their high tolerance of process variations. We have demonstrated and compared two processing schemes, the self-aligned ohmic (SAO) process and the self-aligned implant (SAI) process, for the fabrication of se mico nducto r-"i nsu lato r"-se mico nducto r FETs (SISFET) . The SlSFETs were found to have highly uniform threshold voltages with little backg ati ng effect.