Design and performance evaluation of an adaptive cache coherence protocol

Abstract

In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically, depending on the transfer mode, so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event-driven simulation, and its results show a 58% decrease in the data traffic and a 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about a 56% improvement in the execution time.