Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741143
Chia-Lien Chiang, Jan-Jan Wu, Nai-Wei Lin
The paper reports the design of a runtime library for data-parallel programming on clusters of symmetric multiprocessors (SMP clusters). Our design algorithms exploit a hybrid methodology which maps directly to the underlying hierarchical memory system in SMP clusters, by combining two styles of programming methodologies-threads (shared memory programming) within a SMP node and message passing between SMP nodes. This hybrid approach has been used in the implementation of a library for collective communications. The prototype library is implemented based on standard interfaces for threads (pthread) and message passing (MPI). Experimental results on a cluster of Sun UltraSparc-II workstations are reported.
{"title":"Toward supporting data parallel programming on clusters of symmetric multiprocessors","authors":"Chia-Lien Chiang, Jan-Jan Wu, Nai-Wei Lin","doi":"10.1109/ICPADS.1998.741143","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741143","url":null,"abstract":"The paper reports the design of a runtime library for data-parallel programming on clusters of symmetric multiprocessors (SMP clusters). Our design algorithms exploit a hybrid methodology which maps directly to the underlying hierarchical memory system in SMP clusters, by combining two styles of programming methodologies-threads (shared memory programming) within a SMP node and message passing between SMP nodes. This hybrid approach has been used in the implementation of a library for collective communications. The prototype library is implemented based on standard interfaces for threads (pthread) and message passing (MPI). Experimental results on a cluster of Sun UltraSparc-II workstations are reported.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115511439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741020
K. Ng, Zhenghao Wang, R. Muntz, E. C. Shek
Massive database sizes and growing demands for decision support and data mining result in long-running queries in extensible object-relational DBMSs, particularly in decision support and data warehousing analysis applications. Parallelization of query evaluation is often required for acceptable performance, yet queries are frequently processed suboptimally due to (1) only coarse or inaccurate estimates of the query characteristics and database statistics being available prior to query evaluation; (2) changes in system configuration and resource availability during query evaluation. In a distributed environment, dynamically reconfiguring query execution plans (QEPs), which adapts QEPs to the environment as well as to the query characteristics, is a promising means to significantly improve query evaluation performance. Based on an operator classification, we propose an algorithm to coordinate the steps in a reconfiguration and introduce alternatives for execution context checkpointing and restoring. A syntactic extension of SQL to expose the relevant characteristics of user-defined functions in support of dynamic reconfiguration is proposed. An example from the experimental system is presented.
{"title":"On reconfiguring query execution plans in distributed object-relational DBMS","authors":"K. Ng, Zhenghao Wang, R. Muntz, E. C. Shek","doi":"10.1109/ICPADS.1998.741020","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741020","url":null,"abstract":"Massive database sizes and growing demands for decision support and data mining result in long-running queries in extensible object-relational DBMSs, particularly in decision support and data warehousing analysis applications. Parallelization of query evaluation is often required for acceptable performance, yet queries are frequently processed suboptimally due to (1) only coarse or inaccurate estimates of the query characteristics and database statistics being available prior to query evaluation; (2) changes in system configuration and resource availability during query evaluation. In a distributed environment, dynamically reconfiguring query execution plans (QEPs), which adapts QEPs to the environment as well as to the query characteristics, is a promising means to significantly improve query evaluation performance. Based on an operator classification, we propose an algorithm to coordinate the steps in a reconfiguration and introduce alternatives for execution context checkpointing and restoring. A syntactic extension of SQL to expose the relevant characteristics of user-defined functions in support of dynamic reconfiguration is proposed. An example from the experimental system is presented.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114674796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741014
Young-Jin Jang, Chan-Ho Park, Hyon-Soo Lee
Previous neural network processors were configured either into a SIMD or into an instruction systolic array (ISA) ring architecture using the canonical mapping methodology. The disadvantages of these processors are the lack of generality, scalability, programmability and reconfigurability. So, we propose a programmable neuroprocessor whose architecture is dynamically reconfigurable into either SIMD or an ISA ring according to the data dependencies of any neural network model. To improve the computing time, the computation of an activation function, which typically needed tens of cycles in previous processors, can be done in a single cycle by using piecewise linear (PWL) function approximation. Using a simple bus architecture and instruction set, the proposed processor allows the implementation of neural networks larger than the physical processor element array and allows the user to solve any neural network model. We verify these properties with the error backpropagation (EBP) model and estimate the computation time of the proposed processor.
{"title":"A programmable digital neuro-processor design with dynamically reconfigurable pipeline/parallel architecture","authors":"Young-Jin Jang, Chan-Ho Park, Hyon-Soo Lee","doi":"10.1109/ICPADS.1998.741014","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741014","url":null,"abstract":"Previous neural network processors were configured either into a SIMD or into an instruction systolic array (ISA) ring architecture using the canonical mapping methodology. The disadvantages of these processors are the lack of generality, scalability, programmability and reconfigurability. So, we propose a programmable neuroprocessor whose architecture is dynamically reconfigurable into either SIMD or an ISA ring according to the data dependencies of any neural network model. To improve the computing time, the computation of an activation function, which typically needed tens of cycles in previous processors, can be done in a single cycle by using piecewise linear (PWL) function approximation. Using a simple bus architecture and instruction set, the proposed processor allows the implementation of neural networks larger than the physical processor element array and allows the user to solve any neural network model. We verify these properties with the error backpropagation (EBP) model and estimate the computation time of the proposed processor.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116687561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741043
Hee-Dong Park, Yong-Kee Jun
Detecting races is important for debugging shared memory parallel programs, because the races result in unintended nondeterministic executions of the programs. Previous on-the-fly techniques to detect races in programs with inter thread coordination such as ordered synchronization cannot guarantee that the race detected first is not preceded by events that also participate in a race. The paper presents a novel two pass on-the-fly algorithm to detect the first races in such parallel programs. Detecting the first races is important in debugging, because the removal of such races may make other races disappear including those detected first by the previous techniques. Therefore, this technique makes on-the-fly race detection more effective and practical in debugging parallel programs.
{"title":"Detecting the first races in parallel programs with ordered synchronization","authors":"Hee-Dong Park, Yong-Kee Jun","doi":"10.1109/ICPADS.1998.741043","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741043","url":null,"abstract":"Detecting races is important for debugging shared memory parallel programs, because the races result in unintended nondeterministic executions of the programs. Previous on-the-fly techniques to detect races in programs with inter thread coordination such as ordered synchronization cannot guarantee that the race detected first is not preceded by events that also participate in a race. The paper presents a novel two pass on-the-fly algorithm to detect the first races in such parallel programs. Detecting the first races is important in debugging, because the removal of such races may make other races disappear including those detected first by the previous techniques. Therefore, this technique makes on-the-fly race detection more effective and practical in debugging parallel programs.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117225333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741100
T. Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, K. Ootsu, T. Baba
Our research investigates cost and performance characteristics for wormhole routers based on HDL designs. Comparison for dimension order routers and turn model based adaptive routers leads to the following conclusions: (1) static and additional routing information which we propose, such as prior dimension specification and in-order delivery, improves the communication performance; (2) an adaptive routing algorithm must be implemented to satisfy the objective speed of the design (the operation speed of the routers significantly affects the network performance); (3) the virtual channels cancel the improvement not only for the dimension order router but also for the naive implementation of the adaptive routers when they degrade the operation speed.
{"title":"A cost and performance comparison for wormhole routers based on HDL designs","authors":"T. Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, K. Ootsu, T. Baba","doi":"10.1109/ICPADS.1998.741100","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741100","url":null,"abstract":"Our research investigates cost and performance characteristics for wormhole routers based on HDL designs. Comparison for dimension order routers and turn model based adaptive routers leads to the following conclusions: (1) static and additional routing information which we propose, such as prior dimension specification and in-order delivery, improves the communication performance; (2) an adaptive routing algorithm must be implemented to satisfy the objective speed of the design (the operation speed of the routers significantly affects the network performance); (3) the virtual channels cancel the improvement not only for the dimension order router but also for the naive implementation of the adaptive routers when they degrade the operation speed.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"25 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120999804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741050
Yuzhong Sun, P. Cheung, X. Lin, Keqin Li
With respect to scalability and arbitrary topologies of the underlying networks in multiprogramming and multithread environments, fault tolerance in acknowledged ATAB and concurrent communications become a challenge to reliable general wormhole routing multicomputers with arbitrary topologies. In this paper, the virtual ring tree (VRT) is proposed to deal with the challenge. A single startup is needed in the two proposed algorithms by a simple virtual node space, which also reduces the complexity of routing at intermediate steps of ATAB algorithms and re-beginning an ATAB, by cacheable virtual channels. The proposed algorithm can automatically handle static faults in networks.
{"title":"Fault tolerant all-to-all broadcast in general interconnection networks","authors":"Yuzhong Sun, P. Cheung, X. Lin, Keqin Li","doi":"10.1109/ICPADS.1998.741050","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741050","url":null,"abstract":"With respect to scalability and arbitrary topologies of the underlying networks in multiprogramming and multithread environments, fault tolerance in acknowledged ATAB and concurrent communications become a challenge to reliable general wormhole routing multicomputers with arbitrary topologies. In this paper, the virtual ring tree (VRT) is proposed to deal with the challenge. A single startup is needed in the two proposed algorithms by a simple virtual node space, which also reduces the complexity of routing at intermediate steps of ATAB algorithms and re-beginning an ATAB, by cacheable virtual channels. The proposed algorithm can automatically handle static faults in networks.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741134
Shien-Ching Hwang, Gen-Huey Chen
The cycle partition problem and the pancycle problem on butterfly graphs are studied in this paper. Suppose G=(V,E) is a graph and {V/sub 1/,V/sub 2/,...,V/sub s/} is a partition of V. We say that {V/sub 1/,V/sub 2/,...,V/sub s/} forms a cycle partition of G if each subgraph of G induced by V/sub 1/ contains a cycle of length |V/sub i/|, where 1/spl les/i/spl les/s. A cycle partition {V/sub 1/,V/sub 2/,...,V/sub s/} is /spl lambda/-uniform if |V/sub 1/|=|V/sub 2/|=...=|V/sub s/|=/spl lambda/. G has /spl lambda/-complete uniform cycle partitions if G has m/spl lambda/-uniform cycle partitions for all 1/spl les/m/spl les/(r+n)/2 and m dividing |V|//spl lambda/. Let BF(k,r) denote the r-dimensional k-ary butterfly graph. For the cycle partition problem, we construct a lot of uniform cycle partitions for BF(k,r). Besides, we construct r-complete uniform cycle partitions for BF(2,r), and kr-complete uniform cycle partitions for BF(k,r). For the pancycle problem, given any pair of n and r we can determine if there exists a cycle of length n in BF(2,r), and construct it if it exists. The results of this paper reveal that the butterfly graphs are superior in embedding rings. They can embed rings of almost all possible lengths. Besides, there are many situations in which they can embed the most rings of the same length.
本文研究了蝴蝶图上的环划分问题和环问题。假设G=(V,E)是一个图，并且{V/下标1/，V/下标2/，…，V/下标s/}是V的分划，我们说{V/下标1/，V/下标2/，…，如果由V/sub 1/引起的G的每个子图包含一个长度为|V/sub i/|的循环，其中1/spl小于/i/spl小于/s，则V/sub s/}形成G的循环划分。循环分区{V/sub 1/，V/sub 2/，…, V /子s /} / splλ/制服如果| V /订阅1 / | = | V /子2 / | =…=|V/sub /|=/spl lambda/。G有/spl lambda/-完全均匀循环分区如果G有m/spl lambda/-均匀循环分区对于所有1/spl les/m/spl les/(r+n)/2和m除以|V|//spl lambda/。设BF(k,r)表示r维k元蝴蝶图。对于循环划分问题，我们构造了BF(k,r)的许多一致循环划分。此外，我们构造了BF(2,r)的r-完全一致循环分区和BF(k,r)的r-完全一致循环分区。对于环问题，给定任意一对n和r，我们可以确定BF(2,r)中是否存在长度为n的环，如果存在则构造它。结果表明，蝴蝶图在嵌入环方面具有优越性。它们可以嵌入几乎所有可能长度的环。此外，在许多情况下，它们可以嵌入相同长度的最多的环。
{"title":"Two problems on butterfly graphs","authors":"Shien-Ching Hwang, Gen-Huey Chen","doi":"10.1109/ICPADS.1998.741134","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741134","url":null,"abstract":"The cycle partition problem and the pancycle problem on butterfly graphs are studied in this paper. Suppose G=(V,E) is a graph and {V/sub 1/,V/sub 2/,...,V/sub s/} is a partition of V. We say that {V/sub 1/,V/sub 2/,...,V/sub s/} forms a cycle partition of G if each subgraph of G induced by V/sub 1/ contains a cycle of length |V/sub i/|, where 1/spl les/i/spl les/s. A cycle partition {V/sub 1/,V/sub 2/,...,V/sub s/} is /spl lambda/-uniform if |V/sub 1/|=|V/sub 2/|=...=|V/sub s/|=/spl lambda/. G has /spl lambda/-complete uniform cycle partitions if G has m/spl lambda/-uniform cycle partitions for all 1/spl les/m/spl les/(r+n)/2 and m dividing |V|//spl lambda/. Let BF(k,r) denote the r-dimensional k-ary butterfly graph. For the cycle partition problem, we construct a lot of uniform cycle partitions for BF(k,r). Besides, we construct r-complete uniform cycle partitions for BF(2,r), and kr-complete uniform cycle partitions for BF(k,r). For the pancycle problem, given any pair of n and r we can determine if there exists a cycle of length n in BF(2,r), and construct it if it exists. The results of this paper reveal that the butterfly graphs are superior in embedding rings. They can embed rings of almost all possible lengths. Besides, there are many situations in which they can embed the most rings of the same length.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116430919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741127
Hung-Chang Hsiao, C. King
Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. We study the design strategy for cache depot that: enhances the network interface of each node to include a depot cache, which stores those extra memory blocks for other nodes; and employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.
{"title":"Performance evaluation of cache depot on CC-NUMA multiprocessors","authors":"Hung-Chang Hsiao, C. King","doi":"10.1109/ICPADS.1998.741127","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741127","url":null,"abstract":"Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. We study the design strategy for cache depot that: enhances the network interface of each node to include a depot cache, which stores those extra memory blocks for other nodes; and employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122349780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741033
K. Hasegawa, H. Higaki, M. Takizawa
In object-based systems, objects supporting abstract methods are replicated to increase the performance, reliability and availability. We discuss a novel object-based locking (OBL) protocol to lock replicas of objects by extending the quorum-based protocol for read and write to abstract methods. Unless two methods conflict, subsets of the replicas locked by the methods do not intersect even if the methods change the replicas. Methods not computed on a replica A but computed on another replica are computed on A when a method conflicting with the methods are issued to A in the OBL protocol. We newly propose a version vector to identify what methods are computed on a replica.
{"title":"Object replication using version vector","authors":"K. Hasegawa, H. Higaki, M. Takizawa","doi":"10.1109/ICPADS.1998.741033","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741033","url":null,"abstract":"In object-based systems, objects supporting abstract methods are replicated to increase the performance, reliability and availability. We discuss a novel object-based locking (OBL) protocol to lock replicas of objects by extending the quorum-based protocol for read and write to abstract methods. Unless two methods conflict, subsets of the replicas locked by the methods do not intersect even if the methods change the replicas. Methods not computed on a replica A but computed on another replica are computed on A when a method conflicting with the methods are issued to A in the OBL protocol. We newly propose a version vector to identify what methods are computed on a replica.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114250183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741133
Hung-Yi Chang, Rong-Jaye Chen
In this paper we propose the incrementally extensible folded hypercube (IEFH) graph as a new class of interconnection networks for an arbitrary number of nodes. We show that this system is optimal fault tolerant and almost regular (i.e., the difference between the maximum and the minimum degree of nodes is at most one.). The diameter of this topology is half that of the incomplete hypercube (IH), the supercube, or the IEH graph. We also devise a simple routing algorithm for the IEFH graph. Further we embed cycles and complete binary trees into this graph optimally.
{"title":"Incrementally extensible folded hypercube graphs","authors":"Hung-Yi Chang, Rong-Jaye Chen","doi":"10.1109/ICPADS.1998.741133","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741133","url":null,"abstract":"In this paper we propose the incrementally extensible folded hypercube (IEFH) graph as a new class of interconnection networks for an arbitrary number of nodes. We show that this system is optimal fault tolerant and almost regular (i.e., the difference between the maximum and the minimum degree of nodes is at most one.). The diameter of this topology is half that of the incomplete hypercube (IH), the supercube, or the IEH graph. We also devise a simple routing algorithm for the IEFH graph. Further we embed cycles and complete binary trees into this graph optimally.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117029666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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