PSL assertion checkers synthesis with ASM based HLS tool ABELITE

2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI:10.1109/LATW.2012.6261251

M. Jenihhin, S. Baranov, J. Raik, Valentin Tihhomirov

引用次数: 4

Abstract

This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.

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使用基于ASM的HLS工具ABELITE合成PSL断言检查器

本文提出了一种从属性规范语言(PSL)中描述的时态断言中合成硬件检查器的新方法。该方法利用基于算法状态机(asm)的高级综合(HLS)工具ABELITE。它的目标是创建功能上和时间上正确的检查器，这些检查器在仿真期间提供全面的断言检查调试信息。论文贡献包括一种将PSL断言转换为ASM表示的新方法，以及HLS工具ABELITE应用程序用于正确构造断言生成的新方法。实验结果证明了该方法的可行性和有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 13th Latin American Test Workshop (LATW)

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