A 10.7-µJ/frame 88% Accuracy CIFAR-10 Single-chip Neuromorphic FPGA Processor Featuring Various Nonlinear Functions of Dendrites in Human Cerebrum

IF 2.8 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Micro Pub Date : 2023-11-01 DOI:10.1109/mm.2023.3315676
Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa
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Abstract

A neuromorphic architecture is suitable for low-power tiny-ML processors. However, the large number of synapses utilized in recent deep neural networks require multi-chip implementation, resulting in large power consumption due to chip-to-chip interfaces. Here, we present a 10.7-µJ/frame single-chip neuromorphic FPGA processor. To reduce the required hardware resources, we have developed two techniques. The first is a dendrite-inspired nonlinear neural network (dNNN) that mimics various nonlinear functions of dendrite spines in the human cerebrum. The second is a line scan-based architecture that reduces the total amount of hardware resources. The 14-layer convolutional neural network, which achieves an 88% accuracy with the CIFAR-10 dataset, was implemented on a single FPGA board. Compared to a state-of-the-art spiking CNNbased neuromorphic FPGA processor, the energy efficiency of the proposed architecture is improved by a factor of 94.4 while achieving a 6% better classification accuracy.
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10.7µJ/帧88%精度的CIFAR-10单片神经形态FPGA处理器,具有多种人脑树突非线性功能
神经形态架构适用于低功耗微型ml处理器。然而,最近深度神经网络中使用的大量突触需要多芯片实现,由于芯片间接口导致功耗大。在这里,我们提出了一个10.7µJ/帧的单片神经形态FPGA处理器。为了减少所需的硬件资源,我们开发了两种技术。第一种是树突启发的非线性神经网络(dNNN),它模仿人类大脑中树突棘的各种非线性功能。第二种是基于行扫描的体系结构,它减少了硬件资源的总量。该14层卷积神经网络在单个FPGA板上实现,在CIFAR-10数据集上实现了88%的准确率。与最先进的基于cnn的神经形态FPGA处理器相比,该架构的能效提高了94.4倍,分类准确率提高了6%。
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来源期刊
IEEE Micro
IEEE Micro 工程技术-计算机:软件工程
CiteScore
7.50
自引率
0.00%
发文量
164
审稿时长
>12 weeks
期刊介绍: IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.
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