{"title":"A 10.7-µJ/frame 88% Accuracy CIFAR-10 Single-chip Neuromorphic FPGA Processor Featuring Various Nonlinear Functions of Dendrites in Human Cerebrum","authors":"Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa","doi":"10.1109/mm.2023.3315676","DOIUrl":null,"url":null,"abstract":"A neuromorphic architecture is suitable for low-power tiny-ML processors. However, the large number of synapses utilized in recent deep neural networks require multi-chip implementation, resulting in large power consumption due to chip-to-chip interfaces. Here, we present a 10.7-µJ/frame single-chip neuromorphic FPGA processor. To reduce the required hardware resources, we have developed two techniques. The first is a dendrite-inspired nonlinear neural network (dNNN) that mimics various nonlinear functions of dendrite spines in the human cerebrum. The second is a line scan-based architecture that reduces the total amount of hardware resources. The 14-layer convolutional neural network, which achieves an 88% accuracy with the CIFAR-10 dataset, was implemented on a single FPGA board. Compared to a state-of-the-art spiking CNNbased neuromorphic FPGA processor, the energy efficiency of the proposed architecture is improved by a factor of 94.4 while achieving a 6% better classification accuracy.","PeriodicalId":13100,"journal":{"name":"IEEE Micro","volume":"28 ","pages":"0"},"PeriodicalIF":2.8000,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Micro","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/mm.2023.3315676","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
A neuromorphic architecture is suitable for low-power tiny-ML processors. However, the large number of synapses utilized in recent deep neural networks require multi-chip implementation, resulting in large power consumption due to chip-to-chip interfaces. Here, we present a 10.7-µJ/frame single-chip neuromorphic FPGA processor. To reduce the required hardware resources, we have developed two techniques. The first is a dendrite-inspired nonlinear neural network (dNNN) that mimics various nonlinear functions of dendrite spines in the human cerebrum. The second is a line scan-based architecture that reduces the total amount of hardware resources. The 14-layer convolutional neural network, which achieves an 88% accuracy with the CIFAR-10 dataset, was implemented on a single FPGA board. Compared to a state-of-the-art spiking CNNbased neuromorphic FPGA processor, the energy efficiency of the proposed architecture is improved by a factor of 94.4 while achieving a 6% better classification accuracy.
期刊介绍:
IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.