Abhas Mehta, Hisashi Shichijo, Jungwoo Joh, Chang Suh, Moon Kim
{"title":"Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs","authors":"Abhas Mehta, Hisashi Shichijo, Jungwoo Joh, Chang Suh, Moon Kim","doi":"10.1149/11202.0009ecst","DOIUrl":null,"url":null,"abstract":"This work describes the cause-effect-based degradation process of the p-GaN gate in Enhancement-mode (E-mode) GaN High Electron Mobility Transistors (HEMTs) using gate stressing and failure analysis (FA). We found no correlation between time-to-fail and initial gate current (I G0 ). Instead, a higher impact of temperature was found on the gate current of the device (I G ) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, the gate shows a multi-stage failure. The breakdown starts with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. The metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress.","PeriodicalId":11473,"journal":{"name":"ECS Transactions","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ECS Transactions","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1149/11202.0009ecst","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work describes the cause-effect-based degradation process of the p-GaN gate in Enhancement-mode (E-mode) GaN High Electron Mobility Transistors (HEMTs) using gate stressing and failure analysis (FA). We found no correlation between time-to-fail and initial gate current (I G0 ). Instead, a higher impact of temperature was found on the gate current of the device (I G ) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, the gate shows a multi-stage failure. The breakdown starts with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. The metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress.