Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration

IF 3 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Sustainable Computing Pub Date : 2023-09-11 DOI:10.1109/TSUSC.2023.3313880
Ke Wang;Hao Zheng;Jiajun Li;Ahmed Louri
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Abstract

While current Graph Convolutional Networks (GCNs) accelerators have achieved notable success in a wide range of application domains, these GCN accelerators can not support various intra- and inter- GCN dataflows or adapt to diverse GCN applications. In this paper, we propose Morph-GCNX, a flexible GCN accelerator architecture for high-performance and energy-efficient GCN execution. The proposed design consists of a flexible Processing Element (PE) array that can be partitioned at runtime and adapt to the computational needs of different layers within a GCN or multiple concurrent GCNs. The proposed Morph-GCNX also consists of a morphable interconnection design to support a wide range of GCN dataflows with various parallelization and data reuse strategies for GCN execution. We also propose a hardware-application co-exploration technique that explores the GCN and hardware design spaces to identify the best PE partition, workload allocation, dataflow, and interconnection configurations, with the goal of improving overall performance and energy. Simulation results show that the proposed Morph-GCNX architecture achieves 18.8×, 2.9×, 1.9×, 1.8×, and 2.5× better performance, reduces DRAM accesses by a factor of 10.8×, 3.7×, 2.2×, 2.5×, and 1.3×, and improves energy consumption by 13.2×, 5.6×, 2.1×, 2.5×, and 1.3×, as compared to prior designs including HyGCN, AWB-GCN, LW-GCN, GCoD, and GCNAX, respectively.
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Morph-GCNX:高性能、高能效图卷积网络加速通用架构
虽然目前的图卷积网络(GCN)加速器在广泛的应用领域取得了显著的成功,但这些 GCN 加速器无法支持各种 GCN 内部和 GCN 之间的数据流,也无法适应各种 GCN 应用。在本文中,我们提出了一种灵活的 GCN 加速器架构 Morph-GCNX,用于高性能和高能效的 GCN 执行。拟议的设计由灵活的处理元件(PE)阵列组成,可在运行时进行分区,以适应 GCN 内不同层或多个并发 GCN 的计算需求。拟议的 Morph-GCNX 还包括一个可变形的互连设计,以支持各种 GCN 数据流,并为 GCN 执行提供各种并行化和数据重用策略。我们还提出了一种硬件应用共同探索技术,该技术可探索 GCN 和硬件设计空间,以确定最佳 PE 分区、工作负载分配、数据流和互连配置,从而提高整体性能和能耗。仿真结果表明,所提出的 Morph-GCNX 架构的性能分别提高了 18.8 倍、2.9 倍、1.9 倍、1.8 倍和 2.5 倍,DRAM 访问量分别减少了 10.8 倍、3.7 倍、2.与之前的设计(包括 HyGCN、AWB-GCN、LW-GCN、GCoD 和 GCNAX)相比,性能分别提高了 18.8 倍、2.9 倍、1.9 倍、1.8 倍和 2.5 倍,DRAM 访问次数分别减少了 10.8 倍、3.7 倍、2.2 倍、2.5 倍和 1.3 倍,能耗分别降低了 13.2 倍、5.6 倍、2.1 倍、2.5 倍和 1.3 倍。
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来源期刊
IEEE Transactions on Sustainable Computing
IEEE Transactions on Sustainable Computing Mathematics-Control and Optimization
CiteScore
7.70
自引率
2.60%
发文量
54
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