Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators

IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-09-14 DOI:10.1109/JETCAS.2023.3315561
Mikail Yayla;Fabio Frustaci;Fanny Spagnolo;Jian-Jia Chen;Hussam Amrouch
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Abstract

For accelerating Binarized Neural Networks (BNNs), analog computing-based crossbar accelerators, utilizing XNOR gates and additional interface circuits, have been proposed. Such accelerators demand a large amount of analog-to-digital converters (ADCs) and registers, resulting in expensive designs. To increase the inference efficiency, the state of the art divides the interface circuit into an Analog Path (AP), utilizing (cheap) analog comparators, and a Digital Path (DP), utilizing (expensive) ADCs and registers. During BNN execution, a certain path is selectively triggered. Ideally, as inference via AP is more efficient, it should be triggered as often as possible. However, we reveal that, unless the number of weights is very small, the AP is rarely triggered. To overcome this, we propose a novel BNN inference scheme, called Local Thresholding Approximation (LTA). It approximates the global thresholdings in BNNs by local thresholdings. This enables the use of the AP through most of the execution, which significantly increases the interface circuit efficiency. In our evaluations with two BNN architectures, using LTA reduces the area by 42x and 54x, the energy by 2.7x and 4.2x, and the latency by 3.8x and 1.15x, compared to the state-of-the-art crossbar-based BNN accelerators.
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释放 BNN 的效率:基于模拟的硬件加速器的全局局部阈值法
为了加速二值化神经网络(BNN),有人提出了基于模拟计算的交叉条加速器,利用 XNOR 门和额外的接口电路。这类加速器需要大量模数转换器(ADC)和寄存器,导致设计成本高昂。为了提高推理效率,最新技术将接口电路分为利用(廉价)模拟比较器的模拟路径(AP)和利用(昂贵)模数转换器和寄存器的数字路径(DP)。在 BNN 执行过程中,会选择性地触发某个路径。理想情况下,由于通过 AP 进行推理效率更高,因此应尽可能频繁地触发 AP。然而,我们发现,除非权重的数量非常小,否则 AP 很少被触发。为了克服这一问题,我们提出了一种新颖的 BNN 推理方案,称为局部阈值近似(LTA)。它通过局部阈值来近似 BNN 中的全局阈值。这样就能在大部分执行过程中使用 AP,从而显著提高接口电路的效率。在我们使用两种 BNN 架构进行的评估中,与最先进的基于交叉条的 BNN 加速器相比,使用 LTA 的面积分别减少了 42 倍和 54 倍,能耗分别减少了 2.7 倍和 4.2 倍,延迟分别减少了 3.8 倍和 1.15 倍。
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来源期刊
CiteScore
8.50
自引率
2.20%
发文量
86
期刊介绍: The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.
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Introducing IEEE Collabratec Table of Contents IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors IEEE Circuits and Systems Society Information IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information
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