Pub Date : 2025-12-23DOI: 10.1109/JETCAS.2025.3637354
Qin-Fen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen
{"title":"Guest Editorial: 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part II","authors":"Qin-Fen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen","doi":"10.1109/JETCAS.2025.3637354","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3637354","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"509-513"},"PeriodicalIF":3.8,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313749","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS): A New Chapter Begins","authors":"Chi-Tsun Cheng;Erivelton Nepomuceno;Manisha Guduri","doi":"10.1109/JETCAS.2025.3632497","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3632497","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"507-508"},"PeriodicalIF":3.8,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313750","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/JETCAS.2025.3638227
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information","authors":"","doi":"10.1109/JETCAS.2025.3638227","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3638227","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"C2-C2"},"PeriodicalIF":3.8,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313746","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/JETCAS.2025.3638225
{"title":"IEEE Journal on Emerging and Selected Topics","authors":"","doi":"10.1109/JETCAS.2025.3638225","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3638225","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"674-674"},"PeriodicalIF":3.8,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313747","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/JETCAS.2025.3638083
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","authors":"","doi":"10.1109/JETCAS.2025.3638083","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3638083","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"C3-C3"},"PeriodicalIF":3.8,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313700","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.
{"title":"Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging","authors":"Hongwei Liu;Yuan Du;Bo Pu;Guojun Yuan;Yuhang Liu;Linji Zheng;Pengchao Wang;An Yang;Yu Li;Chengming Yu;Fei Guo;Xiaoteng Zhao;Xuqiang Zheng;He Sun;Yongfu Li;Shaolin Xiang;Qinfen Hao","doi":"10.1109/JETCAS.2025.3636408","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3636408","url":null,"abstract":"Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"514-536"},"PeriodicalIF":3.8,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11265742","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1109/JETCAS.2025.3611595
Mohammad Amin Mahdian;Ebadollah Taheri;Mahdi Nikdast
Silicon photonic (SiPh) interposers offer a promising solution to overcome the bandwidth, latency, and energy limitations of electrical interconnects in chiplet-based systems. By enabling dense Wavelength Division Multiplexing (WDM) and high-speed optical signaling, they support scalable and efficient inter-chiplet communication. However, conventional SiPh interposer architectures face critical challenges, including fabrication-induced yield loss due to active photonic integration, and performance degradation from vertical link misalignments during packaging. This paper introduces MARVEL, a scalable and resilient SiPh interposer network that addresses these challenges through architectural and algorithmic innovations. MARVEL employs a passive interposer design, avoiding yield-limiting active components, and proposes to use optical vertical links (OVLs) to provide direct optical connections between chiplets and a centralized optical circuit switch (OCS). To mitigate the effects of packaging-induced misalignment, MARVEL incorporates redundancy-aware OVL selection using lightweight, reconfigurable on-chip switches. A dynamic in situ characterization protocol ranks available OVLs by loss, enabling the system to route traffic through the best performing links. This mechanism ensures 100% system reachability under modeled manufacturing variations. Additionally, MARVEL introduces a loss-aware recursive backtracking routing algorithm with precomputed lookup tables (LUTs) to optimize switch configurations for reduced insertion loss and tuning power. Comprehensive evaluations—including analytical modeling, Monte Carlo-based variability analysis, and discrete-event network simulation—show that MARVEL achieves up to 82% latency reduction over bus-based architectures and up to 86% improvement compared to prior work under synthetic traffic. On PARSEC benchmark workloads, MARVEL reduces latency by up to 75% while delivering approximately 10% total power savings. These results demonstrate MARVEL’s potential as a robust, energy-efficient, and scalable interposer architecture for next-generation heterogeneous computing platforms, including AI accelerators, high-performance computing (HPC), and data center systems.
{"title":"MARVEL: A Reconfigurable Chiplet-Integrated Photonic Interposer With Optical Vertical Links and Robust Misalignment Tolerance","authors":"Mohammad Amin Mahdian;Ebadollah Taheri;Mahdi Nikdast","doi":"10.1109/JETCAS.2025.3611595","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3611595","url":null,"abstract":"Silicon photonic (SiPh) interposers offer a promising solution to overcome the bandwidth, latency, and energy limitations of electrical interconnects in chiplet-based systems. By enabling dense Wavelength Division Multiplexing (WDM) and high-speed optical signaling, they support scalable and efficient inter-chiplet communication. However, conventional SiPh interposer architectures face critical challenges, including fabrication-induced yield loss due to active photonic integration, and performance degradation from vertical link misalignments during packaging. This paper introduces MARVEL, a scalable and resilient SiPh interposer network that addresses these challenges through architectural and algorithmic innovations. MARVEL employs a passive interposer design, avoiding yield-limiting active components, and proposes to use optical vertical links (OVLs) to provide direct optical connections between chiplets and a centralized optical circuit switch (OCS). To mitigate the effects of packaging-induced misalignment, MARVEL incorporates redundancy-aware OVL selection using lightweight, reconfigurable on-chip switches. A dynamic in situ characterization protocol ranks available OVLs by loss, enabling the system to route traffic through the best performing links. This mechanism ensures 100% system reachability under modeled manufacturing variations. Additionally, MARVEL introduces a loss-aware recursive backtracking routing algorithm with precomputed lookup tables (LUTs) to optimize switch configurations for reduced insertion loss and tuning power. Comprehensive evaluations—including analytical modeling, Monte Carlo-based variability analysis, and discrete-event network simulation—show that MARVEL achieves up to 82% latency reduction over bus-based architectures and up to 86% improvement compared to prior work under synthetic traffic. On PARSEC benchmark workloads, MARVEL reduces latency by up to 75% while delivering approximately 10% total power savings. These results demonstrate MARVEL’s potential as a robust, energy-efficient, and scalable interposer architecture for next-generation heterogeneous computing platforms, including AI accelerators, high-performance computing (HPC), and data center systems.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"619-633"},"PeriodicalIF":3.8,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/JETCAS.2025.3600772
Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen
{"title":"Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part I","authors":"Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen","doi":"10.1109/JETCAS.2025.3600772","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3600772","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"362-367"},"PeriodicalIF":3.8,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/JETCAS.2025.3603800
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors","authors":"","doi":"10.1109/JETCAS.2025.3603800","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3603800","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"506-506"},"PeriodicalIF":3.8,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11164806","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/JETCAS.2025.3603804
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","authors":"","doi":"10.1109/JETCAS.2025.3603804","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3603804","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"C3-C3"},"PeriodicalIF":3.8,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165123","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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