Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications

None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K
{"title":"Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications","authors":"None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K","doi":"10.29292/jics.v18i2.691","DOIUrl":null,"url":null,"abstract":"In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.29292/jics.v18i2.691","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0

Abstract

In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
信号处理应用中基于多路复用器的误差高效定宽加法器树设计
在大量的混合媒体应用中,由于感知能力的小范围,人类不一定能识别无错误或错误的输出。关键信息仍然可以从略微不精确的输出中获得。利用这一点,许多算法,如数字信号处理(DSP),离散余弦变换(DCT),运动补偿(MC)使用近似计算,同时仍然保持可观的计算精度。当考虑到数据处理算法时,加法器通过管理系统的功耗和面积利用率在算术模块中起着重要的作用。提出了一种用于近似计算的固定宽度加法器树设计,以面积和精度之间的权衡作为分析的基础。与全宽度加法器树、FX-AT-PT和FX-AT-DT相比,我们的设计分别使用了12.42%、18.17%和5.05%的面积。此外,与FX-AT-DT、TFX-AT和ITFX-AT相比,该设计在N = 8、16时的最大误差距离(MED)分别为33.33%、29.03%、63.64%、65.63%和38.46%、35.29%。为了解决截断引起的误差,提出的设计采用了基于多的基数-4相加和偏差估计。此外,为了检查误差性能,我们将所提出的设计和其他一些现有设计合并到Walsh-Hadamard变换(WHT)中,以处理具有不同度量的图像并比较图像的峰值信噪比(PSNR)。我们观察到,与ITFX-AT相比,所提出的设计在PSNR评分上有显着改善,并保持与FX-AT-PT相似的评分。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Journal of Integrated Circuits and Systems
Journal of Integrated Circuits and Systems Engineering-Electrical and Electronic Engineering
CiteScore
0.90
自引率
0.00%
发文量
39
期刊介绍: This journal will present state-of-art papers on Integrated Circuits and Systems. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems. The Journal of Integrated Circuits and Systems is published through Special Issues on subjects to be defined by the Editorial Board. Special issues will publish selected papers from both Brazilian Societies annual conferences, SBCCI - Symposium on Integrated Circuits and Systems and SBMicro - Symposium on Microelectronics Technology and Devices.
期刊最新文献
Analysis of biosensing performance of Trench Double Gate Junctionless Field Effect Transistor Alternative approach to design Dibit-based XOR and XNOR gate A Low Power R-peak Detector Clocked at Signal Sampling Rate Impact of the gate work function on the experimental I-V characteristics of MOS solar cells simulated with the Sentaurus TCAD software Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1