In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlabsoftware and also quality factor, contrast, and extinction ratios are calculated for this design.
{"title":"Alternative approach to design Dibit-based XOR and XNOR gate","authors":"Surajit Bosu, Baibaswata Bhattacharjee","doi":"10.29292/jics.v19i1.794","DOIUrl":"https://doi.org/10.29292/jics.v19i1.794","url":null,"abstract":"In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlabsoftware and also quality factor, contrast, and extinction ratios are calculated for this design.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Odilon O. Dutra, Luís H. C. Ferreira, Gustavo D. Colletta, Leonardo B. Zoccal
This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.
本文介绍了一种在 FPGA 中实现的实时、低功耗 R 峰检测器。与其他实现方法不同的是，它以相同的信号采样率运行，而不是像高吞吐量系统的批处理那样利用高时钟频率。这种实现依赖于用于电源线噪声过滤的萨维茨基-戈莱滤波器，以及经过改良的差分运算法（DOM）算法。需要对 DOM 算法进行修改，以便能够在不增加批量处理数据的时钟或不可持续地增加延迟的情况下处理数据。它使用 Savitzky-Golay 数字微分器，省去了进一步的滤波阶段。使用麻省理工学院-BIH 数据库和 Fluke Prosim 8 生命信号模拟器对原型进行了鉴定。所提出的系统具有高度匹配的 R 峰值，而且功耗极低。整个系统的功耗为 260 uW，工作频率为 192Hz，FPGA 型号为 10M50DAF484C7G，属于 Altera 器件的 MAX10 系列。
{"title":"A Low Power R-peak Detector Clocked at Signal Sampling Rate","authors":"Odilon O. Dutra, Luís H. C. Ferreira, Gustavo D. Colletta, Leonardo B. Zoccal","doi":"10.29292/jics.v19i1.798","DOIUrl":"https://doi.org/10.29292/jics.v19i1.798","url":null,"abstract":"This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.
{"title":"Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration","authors":"DP-Rapolu Anil Kumar, K. Sravani, K.Srinivasa Rao","doi":"10.29292/jics.v19i1.784","DOIUrl":"https://doi.org/10.29292/jics.v19i1.784","url":null,"abstract":"The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.
{"title":"High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction","authors":"Tejender Singh, S. Tripathi, Vikram Kumar","doi":"10.29292/jics.v19i1.780","DOIUrl":"https://doi.org/10.29292/jics.v19i1.780","url":null,"abstract":"In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. Theflip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ basedslave latch has been considered for interim data saving during power-gating. The current circuit uses the samewrite current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposedNVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energyconsumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have beenanalyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulationresults show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storingmode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy thanSTT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% lessenergy than SOT-MTJ NVFF and STT-MTJ, respectively.
{"title":"Design and analysis of Voltage-Gated Spin-Orbit Torque (VgSOT) Magnetic Tunnel Junction based Non-Volatile Flip Flop design for Low Energy Applications","authors":"Payal Jangra, Manoj Duhan","doi":"10.29292/jics.v19i1.743","DOIUrl":"https://doi.org/10.29292/jics.v19i1.743","url":null,"abstract":"In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. Theflip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ basedslave latch has been considered for interim data saving during power-gating. The current circuit uses the samewrite current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposedNVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energyconsumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have beenanalyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulationresults show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storingmode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy thanSTT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% lessenergy than SOT-MTJ NVFF and STT-MTJ, respectively.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The structural optimization of the device is used in the present work to demonstrate the improvement of the device sensitivity for a MEMS accelerometer based on capacitive principle due to overlap area change between electrodes. The proof mass of the device is made up of a few parallel fingers those are joined together. Proof mass is supported by flexible mechanical beams that resemble springs is suspended over fixed electrodes and are fastened to the substrate. The greatest displacement that the proof mass can suffer with application of acceleration is determined for the specific construction. The connected beams' width and length were changed, and ANSYS FEA software was used to model the reaction. Sensitivity of the device is analyzed and discussed based on the findings of various device geometry measurements, and suggestions for improving sensitivity are also made. Additionally, a signal conditioning circuit that changes the capacitance to voltage as a result of the proof mass deflecting differently is described. These discoveries might help designers to create capacitive MEMS accelerometers with increased sensitivity.
{"title":"Design and performance analysis of a MEMS Based Area-Variation Capacitive Accelerometer with Readout Circuit","authors":"Mahua Raha Patra, Kalyan Biswas","doi":"10.29292/jics.v19i1.749","DOIUrl":"https://doi.org/10.29292/jics.v19i1.749","url":null,"abstract":"The structural optimization of the device is used in the present work to demonstrate the improvement of the device sensitivity for a MEMS accelerometer based on capacitive principle due to overlap area change between electrodes. The proof mass of the device is made up of a few parallel fingers those are joined together. Proof mass is supported by flexible mechanical beams that resemble springs is suspended over fixed electrodes and are fastened to the substrate. The greatest displacement that the proof mass can suffer with application of acceleration is determined for the specific construction. The connected beams' width and length were changed, and ANSYS FEA software was used to model the reaction. Sensitivity of the device is analyzed and discussed based on the findings of various device geometry measurements, and suggestions for improving sensitivity are also made. Additionally, a signal conditioning circuit that changes the capacitance to voltage as a result of the proof mass deflecting differently is described. These discoveries might help designers to create capacitive MEMS accelerometers with increased sensitivity.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, Piezoresistive Pressure Sensor (PPS) with four Polysilicon piezoresistors on Si3N4 diaphragm with improved sensitivity is successfully designed by using MEMS technology. Sensing is accomplished via deposited polysilicon resistors like metal resistors. The analytical model of PPS is optimized for location and geometry of the piezoresistors and the sensors based on different aspect ratios (both square and rectangular) have been investigated. The performance parameters like maximum deflection, maximum induced stress on the diaphragm have been compared using ANSYS and MATLAB simulation programming based on mathematical model. By interpreting the proper selection of the geometry of a thin Si3N4 diaphragm, the maximum deflection, maximum induced stress and highest sensitivity for this sensor are obtained for the diaphragm when aspect ratio is minimum. It has been found that sensitivity of the sensor is achieved when the piezoresistors are symmetrically placed at 65 m from the edges of the diaphragm. The analysis describes that the sensor based on square diaphragm is more sensitive than the rectangular one. It is influenced more powerfully by diaphragm thickness. The applied pressure range is considered from 0.5 kPa to 40 kPa. From the simulation results, the shape and the sensor design can be optimized for a highly sensitive PPS.
{"title":"Improved Sensitivity of MEMS-based Piezoresistive Pressure Sensor using Silicon Nitride Diaphragm","authors":"K. Das, H. Dutta","doi":"10.29292/jics.v19i1.755","DOIUrl":"https://doi.org/10.29292/jics.v19i1.755","url":null,"abstract":"In this paper, Piezoresistive Pressure Sensor (PPS) with four Polysilicon piezoresistors on Si3N4 diaphragm with improved sensitivity is successfully designed by using MEMS technology. Sensing is accomplished via deposited polysilicon resistors like metal resistors. The analytical model of PPS is optimized for location and geometry of the piezoresistors and the sensors based on different aspect ratios (both square and rectangular) have been investigated. The performance parameters like maximum deflection, maximum induced stress on the diaphragm have been compared using ANSYS and MATLAB simulation programming based on mathematical model. By interpreting the proper selection of the geometry of a thin Si3N4 diaphragm, the maximum deflection, maximum induced stress and highest sensitivity for this sensor are obtained for the diaphragm when aspect ratio is minimum. It has been found that sensitivity of the sensor is achieved when the piezoresistors are symmetrically placed at 65 m from the edges of the diaphragm. The analysis describes that the sensor based on square diaphragm is more sensitive than the rectangular one. It is influenced more powerfully by diaphragm thickness. The applied pressure range is considered from 0.5 kPa to 40 kPa. From the simulation results, the shape and the sensor design can be optimized for a highly sensitive PPS.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rodrigo N. Wuerdig, Leonardo H. Brendler, C. Diniz, Ricardo Reis, Sergio Bampi
This paper presents the physical implementation of the PicoSoC System-on-Chip (SoC) using commercial EDA tools, to use it as a comparison source for future advances in open-source EDA tools for digital implementation flows. The PICORV32 is a simple and versatile microcontroller core that can be used for different applications (e.g., Internet of Things). The whole process entails logical and physical synthesis, design goals aspects, and reports by tools under different working conditions. The Logical and Physical synthesis of the PicoSoC for the X-Fab 180 nm node technology, presented in this work, relies on using the Cadence EDA tools. The microcontrollercore was fully synthesized with and without pads, resulting in a SoC that, including the pads, presents an estimated energy consumption of about 695.3 pJ per operation under nominal conditions.
{"title":"Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology","authors":"Rodrigo N. Wuerdig, Leonardo H. Brendler, C. Diniz, Ricardo Reis, Sergio Bampi","doi":"10.29292/jics.v19i1.769","DOIUrl":"https://doi.org/10.29292/jics.v19i1.769","url":null,"abstract":"This paper presents the physical implementation of the PicoSoC System-on-Chip (SoC) using commercial EDA tools, to use it as a comparison source for future advances in open-source EDA tools for digital implementation flows. The PICORV32 is a simple and versatile microcontroller core that can be used for different applications (e.g., Internet of Things). The whole process entails logical and physical synthesis, design goals aspects, and reports by tools under different working conditions. The Logical and Physical synthesis of the PicoSoC for the X-Fab 180 nm node technology, presented in this work, relies on using the Cadence EDA tools. The microcontrollercore was fully synthesized with and without pads, resulting in a SoC that, including the pads, presents an estimated energy consumption of about 695.3 pJ per operation under nominal conditions.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140392089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Izumi, Marcos Norio Watanabe, Bárbara Siano Alandia, S. G. dos Santos Filho
In this work, the influence of gate work function on the experimental J-VG characteristics of MOS solar cells was investigated with the aid of the Sentaurus TCAD for 2D numer-ical simulations of TiN/SiOxNy/Si Al/SiOxNy/Si and Al/MgO/Mg/SiOxNy/Si structures aiming at solar cells for en-ergy harvesting applications. The increase of the gate work function led to the increase of the reverse current density as pointed out by the Sentaurus TCAD simulations and by the ex-perimental J-VG characteristics. The work functions of Mg, Al, and un-annealed TiN used in the TCAD simulations were 3.7 eV, 4.1 eV, and 4.4 eV, respectively. It was observed that the onset voltage at 0.5 mA/cm2 in the forward-biasing region was at a lower voltage for TiN (~ - 0.06 V) compared to Al (~ - 0.42 V) and the Al/MgO/Mg stack (~ - 0.47 V). On the other hand, the current density increased steeply in the forward biasing for TiN and Al compared to the Al/ MgO/Mg stack gate and the thin MgO layer between Al and Mg worked as a potential barrier in an opposite direction to the potential barrier of the Mg/Si-OxNy/Si structure, which meant an onset voltage lowering for the Al/MgO/Mg/SiOxNy/Si solar cell. For the Al/MgO/Mg stack, the barrier effect of the MgO layer was fitted as a series re-sistance RS = 100 Ω and an equivalent Al/MgO/Mg work func-tion of 4.15 eV considering a substrate doping NA = 1.2x1016 cm-3 and parallel conductance GP = 0. Also, the experimental JxVG characteristic of the Al/SiOxNy/Si cell was fitted for Al work function of 4.10 eV, a series resistance RS = 100 Ω, a parallel resistance RP = 0.02 Ω (GP = 50 S) and a substrate doping NA = 5.5x1015 cm-3. In this case, the high parallel conductance fitted was attributed to the tunneling through the dielectrics as a pre-dominant effect possibly caused by a high concentration of de-fects in the SiOxNy layer. Finally, the MOS solar cell parameters were relatively lower compared to those of commercial outdoor solar cells, but the power generated by the MOS cells reached the mW range, and the conversion efficiency from light energy into electrical energy was higher (12.7%) than the typical values found for energy-harvesting solar cells.
{"title":"Impact of the gate work function on the experimental I-V characteristics of MOS solar cells simulated with the Sentaurus TCAD software","authors":"F. Izumi, Marcos Norio Watanabe, Bárbara Siano Alandia, S. G. dos Santos Filho","doi":"10.29292/jics.v19i1.700","DOIUrl":"https://doi.org/10.29292/jics.v19i1.700","url":null,"abstract":"In this work, the influence of gate work function on the experimental J-VG characteristics of MOS solar cells was investigated with the aid of the Sentaurus TCAD for 2D numer-ical simulations of TiN/SiOxNy/Si Al/SiOxNy/Si and Al/MgO/Mg/SiOxNy/Si structures aiming at solar cells for en-ergy harvesting applications. The increase of the gate work function led to the increase of the reverse current density as pointed out by the Sentaurus TCAD simulations and by the ex-perimental J-VG characteristics. The work functions of Mg, Al, and un-annealed TiN used in the TCAD simulations were 3.7 eV, 4.1 eV, and 4.4 eV, respectively. It was observed that the onset voltage at 0.5 mA/cm2 in the forward-biasing region was at a lower voltage for TiN (~ - 0.06 V) compared to Al (~ - 0.42 V) and the Al/MgO/Mg stack (~ - 0.47 V). On the other hand, the current density increased steeply in the forward biasing for TiN and Al compared to the Al/ MgO/Mg stack gate and the thin MgO layer between Al and Mg worked as a potential barrier in an opposite direction to the potential barrier of the Mg/Si-OxNy/Si structure, which meant an onset voltage lowering for the Al/MgO/Mg/SiOxNy/Si solar cell. For the Al/MgO/Mg stack, the barrier effect of the MgO layer was fitted as a series re-sistance RS = 100 Ω and an equivalent Al/MgO/Mg work func-tion of 4.15 eV considering a substrate doping NA = 1.2x1016 cm-3 and parallel conductance GP = 0. Also, the experimental JxVG characteristic of the Al/SiOxNy/Si cell was fitted for Al work function of 4.10 eV, a series resistance RS = 100 Ω, a parallel resistance RP = 0.02 Ω (GP = 50 S) and a substrate doping NA = 5.5x1015 cm-3. In this case, the high parallel conductance fitted was attributed to the tunneling through the dielectrics as a pre-dominant effect possibly caused by a high concentration of de-fects in the SiOxNy layer. Finally, the MOS solar cell parameters were relatively lower compared to those of commercial outdoor solar cells, but the power generated by the MOS cells reached the mW range, and the conversion efficiency from light energy into electrical energy was higher (12.7%) than the typical values found for energy-harvesting solar cells.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.
{"title":"Analysis of biosensing performance of Trench Double Gate Junctionless Field Effect Transistor","authors":"Palasri Dhar, Soumik Poddar, Sunipa Roy","doi":"10.29292/jics.v19i1.748","DOIUrl":"https://doi.org/10.29292/jics.v19i1.748","url":null,"abstract":"Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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