A Simple and Effective Evaluation Method for Fault-Tolerant Routing Methods in Network-on-Chips

Abstract

—This paper proposes a simple and effective evaluation method for fault-tolerant routing methods developed for Network-on-Chip (NoC)-based many-core processors. To cope with faults which significantly degrade the reliability of communication among cores, a variety of fault-tolerant routing methods have been studied. Those methods have been mainly evaluated in terms of communication performance such as latency and throughput by computer simulations of packet routing. However, such evaluations are not practical in that they cannot reveal the performance difference in executing parallel applications with the fault-tolerant routing methods. The proposed method obtains the information of the target parallel application such as task execution time, communication pattern, and communication amount and incorporates it in the conventional packet routing simulations. With the proposed evaluation method, computer simulations have been conducted to evaluate the performance of four famous fault-tolerant routing methods, i.e., Fcube4, Position Route, Passage-Y, and Passage-XY, using NAS Parallel Benchmarks and the performance difference is revealed in executing parallel programs named Integer Sort (IS) and Fast Fourier Transform (FFT). The results show that, Passage-XY outperforms other methods in both IS and FT, and for the case of IS, Passage-XY can reduce the program execution time by up to about 39%, 56%, and 26% compared with Fcube4, Position Route, and Passage-Y, respectively.