Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage

Abstract

Abstract Based on the 0.18 μ m CMOS process, proposed a new power-rail electrostatic discharge clamp circuit. The proposed circuit can adjust the voltage biased to the big clamp NMOS (M big ) gate by adjusting the width of one MOS transistor, and the feedback path is designed to prolong the response time of M big . The simulation results demonstrated that the voltage biased to the M big of the proposed circuit has a relatively steady state and the M big has a longer response time, which can effectively reduce the damage to the gate oxide layer of the M big with large voltage overshoot. The transmission line pulse test results show that compared to the M big of the conventional circuit, the M big of the proposed circuit has higher trigger voltage, lower on-resistance, and better robustness.