Bonding Property of Flip-Chip Chip-Scale Package with Vacuum Reflow and Thermal Compression Bonding Processes

Abstract

The package-on-package technology has been developed to facilitate high-density integration of semiconductor packaging. As the solder bump pitch is decreased, the void content in solder bump joints increases, thereby decreasing its reliability. Consequently, vacuum reflow (VR) is used to increase void fluidity and decrease void content in micro bump joints. Generally, silicon chips in application processor modules are bonded using thermal compression (TC) bonding, followed by the attachment of passive components through hot air reflow soldering. However, the simultaneous bonding of Si chips and passive components using VR can improve productivity.In this study, we performed TC and VR bonding without additional solder pastes, between an Si chip with a Cu pillar/Sn-2.5Ag bump and a bismaleimide triazine substrate plated with electroless-nickel electroless-palladium immersion-gold. It was observed that the void content at the Si chip solder joints yielded by VR (10.8%) was similar to that yielded by TC (11.2%). Furthermore, the Si chip solder joint of the VR sample was thicker than that of the TC sample. This process also resulted in the formation of the intermetallic compounds Cu₆Sn₅, (Cu,Ni)₆Sn₅, Ag₃Sn, and Ni₃P, at the Si chip solder joints. The results of this study suggest that co-bonding of active and passive components is possible through VR soldering for semiconductor packaging.