M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici
{"title":"A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors","authors":"M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici","doi":"10.1109/LSSC.2023.3324589","DOIUrl":null,"url":null,"abstract":"A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n to 2.8 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n in the 100-Hz to 1-kHz band and from 14.2 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n to 4.6 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"289-292"},"PeriodicalIF":2.2000,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10285376/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3
$\mu \text{V}_{\mathrm{ rms}}$
to 2.8
$\mu \text{V}_{\mathrm{ rms}}$
in the 100-Hz to 1-kHz band and from 14.2
$\mu \text{V}_{\mathrm{ rms}}$
to 4.6
$\mu \text{V}_{\mathrm{ rms}}$
in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.