A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2023-10-13 DOI:10.1109/LSSC.2023.3324589
M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici
{"title":"A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors","authors":"M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici","doi":"10.1109/LSSC.2023.3324589","DOIUrl":null,"url":null,"abstract":"A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n to 2.8 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n in the 100-Hz to 1-kHz band and from 14.2 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n to 4.6 \n<inline-formula> <tex-math>$\\mu \\text{V}_{\\mathrm{ rms}}$ </tex-math></inline-formula>\n in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"289-292"},"PeriodicalIF":2.2000,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10285376/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 $\mu \text{V}_{\mathrm{ rms}}$ to 2.8 $\mu \text{V}_{\mathrm{ rms}}$ in the 100-Hz to 1-kHz band and from 14.2 $\mu \text{V}_{\mathrm{ rms}}$ to 4.6 $\mu \text{V}_{\mathrm{ rms}}$ in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于HDD飞高电阻传感器的0.13 μm BiCMOS、130 mhz带宽消噪接口电路
本文介绍了一种基于闭环偏置和噪声消除技术的全模拟接口电路,该电路采用130纳米BiCMOS技术制造。所提出的接口电路能够精确地偏置传感器并在两个频率范围(低频(LF)范围从dc到375 kHz和高频范围从1 kHz到130 MHz)中读出结果信号。在低频范围内,由于专用的降噪技术,所实现的综合输入参考噪声在100 hz至1 khz频段分别从7.3 $\mu \text{V}_{\mathrm{rms}}$降至2.8 $\mu \text{V}_{\mathrm{rms}}$,在1- 100 khz频段分别从14.2 $\mu \text{V}_{\mathrm{rms}}$降至4.6 $\mu \text{V}_{\mathrm{rms}}$。该芯片的有效面积为1.11 mm2,功耗为172 mW,其中包括传感器偏置所需的36 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
期刊最新文献
Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1